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.25 m, five layer metal cmos process 2.5 v v cc , 2.5/3.3 v drive capable i/o 960 logic cells 248,160 max system gates up to 250 i/o pins twenty 2,304-bit dual port high performance sram blocks 46,100 ram bits ram/rom/fifo wizard for automatic configuration configurable and cascadable ! high performance enhanced i/o (eio): less than 3 ns tco programmable slew rate control programmable i/o standards: lvttl, lvcmos, pci, gtl+, sstl2, and sstl3 eight independent i/o banks three register configurations: input, output, and output enable "#$%&$ nine global clock networks: one dedicated eight programmable 20 quad-net networks: five per quadrant 16 i/o controls: two per i/o bank

memory - dual port ram high speed logic cells 248k gates memory - dual port ram #"" '"(" )(" *+,-./

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0 ## 1,2-0(31,-4#561.2789 the ac specifications are provided from 3 to 3 . . logic cell diagrams and waveforms are provided from , to - .

) 05" 9 # " t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output - 0.257 t su setup time: time the synchronous input of the flip flop must be stable before the active clock edge 0.22 - t hl hold time: time the synchronous input of the flip flop must be stable after the active clock edge 0 - t co clock to out delay: the amount of time taken by the flip flop to output after the active clock edge. - 0.255 t cwhi clock high time: required minimum time the clock stays high 0.46 - t cwlo clock low time: required minimum time that the clock stays low 0.46 - t set set delay: time between when the flip flop is ?set? (high) and when the output is consequently ?set? (high) - 0.18 t reset reset delay: time between when the flip flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.09 t sw set width: time that the set signal remains high/low 0.3 - t rw reset width: time that the reset signal remains high/low 0.3 -

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& '"#$ set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw clk d q t su t hl t co
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*) &! ! &+! , $ #$ #$'" ; logic cells (internal) clock signal generated internally 1.51 ns (max) 1.59 ns (max) i/o ? s (external) clock signal generated externally 2.06 ns (max) 1.73 ns (max) ) , $ #$ " 05" 9 " t pgck global clock pin delay to quad net - 1.34 t bgck global clock buffer delay (quad net to flip flop) - 0.56 quad net programmable clock external clock global clock buffer global clock t pgck t bgck clock select

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" <3" " t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.675 - t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0 - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 - t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.623 - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 4.38 wa wd we wclk re rclk ra rd ram module [9:0] [17:0] [9:0] [17:0] asyncrd
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" 3" " t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.686 - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.243 - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 4.38 # )"
" 3" r pdrd ra to rd: time between when the read address is input and when the data is output - 2.06 t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd

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567 t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd e r q d r q e r q d + - pad output enable register output register input register d
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! ) 05" 9 "/ #!") " t isu input register setup time: time the synchronous input of the flip flop must be stable before the active clock edge 3.12 - t ihl input register hold time: time the synchronous input of the flip flop must be stable after the active clock edge 0 - t ico input register clock to out: time taken by the flip flop to output after the active clock edge - 1.08 t irst input register reset delay: time between when the flip flop is ? reset ? (low) and when the output is consequently ? reset ? (low) - 0.99 t iesu input register clock enable setup time: time ? enable ? must be stable before the active clock edge 0.37 - t ieh input register clock enable hold time: time ? enable ? must be stable after the active clock edge 0 - pad t in , t ini t iclk t isu t sid + - q e d r

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)? " t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.34 t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.42 t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.68 t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.55 t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.61 r clk d q t isu t ihl t ico t iesu t ieh t irst e
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! ) 05" 9 !/ #!") " t outlh output delay low to high (90% of h) - 0.40 t outhl output delay high to low (10% of l) - 0.55 t pzh output delay tri-state to high (90% of h) - 2.94 t pzl output delay tri-state to low (10% of l) - 2.34 t phz output delay high to tri-state - 3.07 t plz output delay low to tri-state - 2.53 t cop clock-to-out delay (does not include clock tree delays) - 3.15 (fast slew) 10.2 (slow slew) pad output register

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27!!&.!89 57 :9 & && rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns 47!!&.!89 57 :%9 & && rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz
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the dc specifications are provided in 3 through 3 : . / !0;.!
0 0 0 ## 0 -0.5 v to 3.6 v #"/#" 20 ma 0 ##! 0 -0.5 v to 4.6 v " 2000 v % 0 2.7 v $ 3/ -65 c to + 150 c "/0 -0.5 v to v ccio +0.5 v "$ 5@;9 3/ -55 c to + 125 c
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) ) " # ?" " " " v cc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v v ccio i/o input tolerance voltage 2.3 3.6 2.3 3.6 2.3 3.6 v ta ambient temperature -55 -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -4 speed grade 0.42 2.3 0.43 2.16 0.47 2.11 n/a -5 speed grade 0.42 1.92 0.43 1.80 0.46 1.76 n/a -6 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.42 1.28 0.43 1.19 0.46 1.16 n/a + ! ! ) #"" " ?" i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance a !!!' 1 ; --8pf i os output short circuit current b 71 !!!! ! + ' !;'4 ' v o = gnd v o = v cc -15 40 -180 210 ma ma i cc d.c. supply current c 6 %6 (6 *
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''# v i, v o = v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio - 0 2 ma i ccio (dif) d.c. supply current on v ccio for differential i/o ---ma i ref d.c. supply current on inref - -10 10 a i pd pad pull-down (programmable) v ccio = 3.6 v - 150 a

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*57=#97= iol vs vol 0 20 40 60 80 100 120 140 160 180 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 supply voltage (v) current (ma) vccio = 3.6v vccio = 3.3v vccio = 3.0v vccio = 2.7v vccio = 2.5v vccio = 2.3v -120 -100 -80 -60 -40 -20 0 20 0. 00 0. 10 0. 30 0. 50 0. 70 0. 90 1. 10 1. 30 1. 50 1. 70 1. 90 2. 10 2. 30 2. 50 2. 70 2. 90 3. 00 3. 10 3. 30 3. 50 3. 60 supply voltage (v) current (ma) vcci/o = 2.3v vcci/o = 2.5v vcci/o = 2.7v vcci/o = 3.3v vcci/o = 3.6v vcci/0 = 3.0v ioh vs voh
8

note: the data provided in 3 8 are jedec and pci specifications ? quicklogic ? devices either meet or exceed these requirements. for data specific to quicklogic i/os, see 3 through 3 : and through 7 . note: all clk and inref pins are clamped to the v cc rail, not the v ccio . therefore, these pins can only be driven up to v cc + 0.3 v. 5!'7!!# % 0 0 0 ! 0 ! ! ! 0 % 0 b 0 % 0 b 0 % 0 b 0 b 0 % lvttl n/a n/a -0.3 0.8 2.0 v ccio + 0.3 0.4 2.4 2.0 -2.0 lvcmos2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.5 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8

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thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 150 o c. to calculate the maximum power dissipation for a device package look up ja from 3 - , pick an appropriate t amax and use: p max = (150o c - t amax )/ ja %,
+ + ! ! $ /" ja 5c# <9d '& 5 9 jc 5c# <9 "#" $ 3)/ . .2- , 516 pbga 20.0 19.0 17.5 16.0 7.0 484 pbga 28.0 26.0 25.0 23.0 9.0 280 lf-pbga 18.5 17.0 15.5 14.0 7.0 208 pqfp 26.0 24.5 23.0 22.0 11.0
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! voltage factor vs. supply voltage 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 supply voltage (v) kv temperature factor vs. operating temperature 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 junction temperature c kt

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& 2!/" e") the basic power equation which best models power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins ,. exhibits the power consumption in an eclipse ql6250 device. the chip was filled with (300) 8-bit counters ? approximately 76% logic cell utilization.
4, ! , illustrates the theoretical worst-case scenarios for 50%, 70%, and 90% utilizations of the 6600-516 package. the resources of the device are divided exactly in half; meaning, for 50% utilization, exactly 50% of the i/os, logic cells, ram blocks, clock network, etc. are utilized. these situations may never occur in a real design, but they do provide a very rough quantitative measure of power consumption when talking in terms of 50% or 70% utilization of an eclipse device. power vs freq. (counter_300) 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 frequency (mhz) power (w)
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, # 1>/ !%4?<*4?<'24? $!+/#. +@ note: to learn more about power consumption, please refer to application note #60 which is located at www.quicklogic.com . power vs. frequency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 300 frequency (mhz) 50% 70% 90% power (w)

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, . ! the following requirements must be met when powering up a device (refer to ,, ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause permanent damage to the device. v ccio must lead v cc when ramping the device. the power supply must be greater than or equal to 400 s to reach v cc . ramping to v cc /v ccio before reaching 400 s can cause the device to behave improperly. a diode is present in-between v cc and v ccio , as shown in ,: .
5! '!9 '9 57 voltage v ccio v cc (v ccio -v cc ) max 400 us v cc v cc v ccio internal logic cells, ram blocks, etc io cells
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microprocessors and application specific integrated circuits (asics) pose many design challenges, not in the least of which concerns the accessibility of test points. the joint test access group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run three required tests along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register

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the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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%567!+.#!, (a/), ! " "" /" tdi/rsi test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused trstb/rro active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag tdo/rco test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g)

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*'!', ! " "" /" i/gclk high-drive input and/or global clock network driver can be configured as either input or global clock i/o(a) input/output pin the i/o pin is a bi-directional pin, configurable to either an input- only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. v cc power supply pin connect to 2.5 v supply v ccio (a) input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v device or a 2.5 v device. the a inside the parenthesis means that v ccio is located in bank a. every i/o pin in bank a will be tolerant of v ccio input signals and will output v ccio level signals. this pin must be connected to either 3.3 v or v cc . gnd ground pin connect to ground pllin pll clock input clock input for pll dedclk dedicated clock pin low skew global clock gndpll ground pin for pll connect to gnd inref(a) differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in 3 8 for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if not needed. pllout pll output pin dedicated pll output pin. otherwise may be left unconnected ioctrl(a) highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. this pin should be tied to gnd or v cc if it is not used.
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/ all unused, general purpose i/o pins can be tied to v cc , gnd, or hiz (high impedance) internally using the configuration editor. this option is given in the bottom-right corner of the placement window. to use the placement editor, choose constraint ? fix placement in the option pull-down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in 3 = . note: x -> number, y -> alphabetical character. !" "'"
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5$ ! -. ''b', ! "% "3"" pllout unused pll output pins must be connected to either v cc or gnd so that their associated input buffer never floats. utilized pll output pins that route the pll clock outside of the chip should not be tied to either v cc or gnd. ioctrl any unused pins of this type must be connected to either v cc or gnd. clk/pllin any unused clock pins should be connected to v cc or gnd. pllrst if a pll module is not used, then the associated pllrst must be connected to v cc ; under normal operation, use it as needed. inref if an i/o bank does not require the use of inref signal the pin should be connected to gnd. ql 6250 - 4 pb516 c quicklogic device eclipse device part number speed grade 4 = quick 5 = fast 6 = faster 7 = fastest operating range c = commercial i = industrial m = military package code pt208 = 208-pin fpbga pt280 = 280-pin fpbga ps484 = 484-pin bga (1.0 mm) pb516 = 516-pin bga (1.27 mm)

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,=.@;"3 4-4,)/, ! ,=.@; "" ,=.@; "" ,=.@; "" ,=.@; "" ,=.@; "" ,=.@; "" ,7bfg #. df%g6,5efg > 57.fg 6+ 567fg 8 567f=g ?: 567fg , )e,f4g # 9 57 fg 5e.f)g 67 567fg - )e ?8 57.fg : 567fg #, 567fg , 57.f)g 6= 567fg + )e ?- 9 57 fg 8 567fg #: 567fg : 567f)g 6> .& 7 9 ?+ 567fg - 567fg #8 567fg 8 567f)g 567f=g = 9 ?7 7 + 57.fg #- 9 57 fg - )e , 567f=g > )e ?= ,.&fg 7 567fg #+ 567fg - 9 : 9 57 f=g . )e ?> 567fg = 567fg #7 567fg + 57.fg 8 567f=g 9 0 ,7bfg > 567fg #= 567fg 7 567fg - 9 , 9 0, )e,fg . df*g #> 567fg = 567fg - )e : 9 0: )e 567fg 567f)g > 567fg + 567fg 8 9 08 567f/g , 567fg , 567f)g ; 567f)g 7 9 57 fg - )e 0- 567f/g : 567fg : 567fg ;, 567f)g = 567fg + 567fg 0+ 57.f/g 8 57.fg 8 567fg ;: 57.f)g > 567fg 7 9 57 fg 07 567f/g - 567fg - 567fg ;8 567f)g 567f=g = 567fg 0= 567f/g + 567fg + 567fg ;- 9 , 567f=g > 567fg 0> 567f/g 7 567fg 7 567fg ;- 9 : 567f=g 3 567f=g 0. dfg = ,.&fg = 567fg ;+ 567fg 8 567f=g 3, 567f=g 0 dfg d6,5ef4g > )e > df-g ;7 567fg - 9 3: 567f/g 0, 567fg @ ,.&f4g . 567fg ;= 567fg - 9 38 567f/g 0: 567fg @, )e 567fg ;> 567fg + 5e.fg 3- 567f/g 08 5e.fg @: 567fg , 567fg 567f)g 7 567fg 3+ 57.f/g 0- 567fg @8 567fg : 5e.fg , 567f)g = 567fg 37 567f/g 0+ 567fg @- 567fg 8 567fg : 567f)g > 567fg 3= 567f/g 07 567fg @+ 5e.fg - 567fg 8 567f)g % 57.f=g 3> 567f/g 0= )e,fg @7 567fg + 567fg - 9 %, 567f=g 3. 567f/g 0> )e @= 567fg 7 567fg - 9 %: 567f=g 3 dfg6,5efg < )e @> 0& = 567fg + 9 %8 567f=g 3, 567fg <, ,.&fg @. df(g > 567fg 7 567fg %- 9 3: 567fg <: 567f/g @ 567fg 567f)g = 567fg %- 9 38 567fg <8 567f/g @, 567fg , 567f)g > 567fg %+ 567fg 3- 567fg <- 567f/g @: 57.fg : 9 57 f)g f 567f)g %7 567fg 3+ 567fg <+ 567f/g @8 567fg 8 567fg f, 567f)g %= 57.fg 37 9 , fg <7 567f/g @- 567fg - )e f: 9 57 f)g %> 57.fg 3= 567fg <= 567f/g @+ 567fg + 9 f8 567f)g 567f=g 3> 567fg <> 5 @7 9 , fg 7 9 f- )e , 567f=g ? 567f/g <. dfg6,5efg @= )e,fg = 9 f- 9 : 57.f=g ?, 567f/g < 567fg @> ,7bf4g > 9 f+ 567fg 8 5e.f=g ?: 9 , fg <, 567fg # 567fg . )e f7 9 57 fg - 9 ?8 567f/g <: 567fg #, 9 , f4g )e f= 567fg - )e ?- 9 57 f/g <8 57.fg #: 567fg , 9 f> 567fg + 567fg ?+ 5e.f/g <- 567fg #8 567fg : 9 6 9 7 567fg ?7 567f/g <+ 567fg #- 9 57 fg 8 )e 6, d = 567fg ?= 567f/g <7 567fg #+ 57.fg - )e 6: 567f)g > 567fg ?> 9 57 f/g <= 567fg #7 567fg + 567fg 68 567f)g 567f=g ?. df4g <> ,7bfg #= 567fg 7 9 57 fg 6- )e , 567f=g ? 9 57 fg #> 9 57 fg = 5e.fg 6- )e : 9 57 f=g ?, 567fg

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8=8@;"3 -,)/, ! 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" e # e 57.f/g ; e f 567f/g dfg d6,5ef4g , ,.&fg #, 567f/g , 567f/g ;, e f, 567f/g , df4g : 567f/g #: 9 , fg : 567f/g ;: 567f/g f: 567f/g : dfg6,5efg 8 567f/g #8 ,7bfg 8 567f/g ;8 567f/g f8 567f/g 8 567f/g - 567f/g #- 567f/g - e ;- 567f/g f- 567f/g - 567f/g + e #+ e + 567f=g ;+ 567f/g f+ 567f/g + 567f/g 7 567f=g #7 567f=g 7 e ;7 )e f7 567f/g 7 )e = 57.f=g #= e = 567f=g ;= 567f=g f= 9 = )e > 567f=g #> 57.f=g > 567f=g ;> 567f=g f> )e > )e . e #. e . 567f=g ;. e f. 9 . )e e # 567f=g 9 ; 567f)g f 9 )e , d #, e , 567f)g ;, )e f, )e , )e : 567f)g #: 567f)g : 567f)g ;: e f: 9 : )e 8 567f)g #8 e 8 e ;8 e f8 )e 8 9 - 567f)g #- 567f)g - 57.f)g ;- 567f)g f- 9 - 9 + e #+ 567f)g + 567f)g ;+ )e f+ 567fg + df(g 7 567f)g #7 e 7 5e.f)g ;7 9 57 fg f7 9 57 fg 7 9 57 fg = 567f)g #= 567f)g = e ;= 567fg f= 567fg = 567fg > 567fg #> 567fg > 567fg ;> 567fg f> 567fg > df-g ,. )e #,. )e,f4g ,. 567fg ;,. 567fg f,. 567fg ,. 567fg , ,7bfg #, 567fg , e ;, 5e.fg f, 567fg , e ,, 567fg #,, 567fg ,, 567fg ;,, 567fg f,, 567fg ,, 567fg @ 567f/g 567f/g 567f/g 567f/g 6 5 567fg @, )e , 567f/g , 5e.f/g , 567f/g 6, 567f/g , 567fg @: )e,fg : 567f/g : e : 567f/g 6: 567f/g : 567fg @8 )e 8 567f/g 8 567f/g 8 567f/g 68 567f/g 8 dfg6,5efg @- 567f/g - 567f/g - 567f/g - 57.f/g 6- 567f/g - e @+ 567f=g + 567f=g + 9 57 f/g + 9 57 f/g 6+ 9 57 f/g + 9 57 fg @7 567f=g 7 e 7 9 57 f=g 7 567f=g 67 e 7 dfg @= 5e.f=g = 567f=g = 567f=g = )e 6= 9 = 9 @> 567f=g > e > 9 57 f=g > 9 6> 9 > 9 @. 567f=g . 567f=g . 567f=g . 9 6. )e . )e @ 567f=g 567f=g 9 57 f=g 9 6 )e )e @, e , 567f)g , 9 57 f)g , )e 6, )e , )e @: e : 567f)g : 567f)g : 9 6: )e : )e @8 e 8 567f)g 8 9 57 f)g 8 9 68 9 8 )e @- e - 57.f)g - e - )e 6- 9 - )e @+ 567f)g + 567f)g + 9 57 f)g + 567fg 6+ e + )e @7 567f)g 7 567f)g 7 e 7 567fg 67 567fg 7 567fg @= 567f)g = 567fg = 567fg = e 6= 567fg = 567fg @> ,.&f4g > 9 , f4g > 567fg > 567fg 6> e > 567fg @,. 567fg ,. 567fg ,. 57.fg ,. 567fg 6,. 567fg ,. df*g @, 567fg , 567fg , 567fg , 567fg 6, 567fg , df%g6,5efg @,, 567fg ,, 567fg ,, 57.fg ,, e 6,, e ,, 0& 5
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% e + 567fg 3> e 0, 567fg <7 e . 567fg %, 567fg 7 e 3. .& 0: 567fg <= 567fg 567fg %: 567fg = 567fg 3 )e 08 567fg <> e , 567fg %8 e > e 3, e 0- 567fg <,. 567fg : 567fg %- 567fg ,. 567fg 3: 567fg 0+ e <, e 8 567fg %+ e , 567fg 38 e 07 567fg <,, 567fg - 567fg %7 e ,, 567fg 3- 567fg 0= 567fg g 567fg + e %= 9 567fg 3+ )e 0> e g, 567fg 7 e %> 9 , 5e.fg 37 567fg 0. 567fg g: 9 , fg = 567fg %. )e : 567fg 3= 567fg 0 e g8 567fg > 567fg % )e 8 567fg 3> e 0, 9 g- 567fg ,. )e,fg %, )e - 567fg 3,. e 0: e g+ 567fg , 567fg %: )e + e 3, 57.fg 08 567fg g7 567fg ,, 567fg %8 9 7 567fg 3,, 567fg 0- 567fg g= 57.fg @ 567fg %- 9 = )e ? 57.fg 0+ 5e.fg g> 567fg @, )e,fg %+ 567fg > 9 ?, 567fg 07 567fg g. 567fg @: ,.&fg %7 9 57 fg . 9 ?: 57.fg 0= 567fg g 567fg @8 567fg %= 567fg )e ?8 567fg 0> 567fg g, e @- 567fg %> 567fg , 9 ?- 567fg 0,. 567fg g: e @+ 567fg %,. 567fg : 9 ?+ 567fg 0, 567fg g8 567fg @7 567fg %, 567fg 8 9 ?7 9 57 fg 0,, 567fg g- 57.fg @= 57.fg %,, 567fg - )e ?= e < 567fg g+ 567fg @> 567fg e + 567fg ?> 9 57 fg <, 567fg g7 567fg @. 567fg , 567fg 7 9 57 fg ?. 567fg <: 567fg g= 567fg @ e : 567fg = 567fg ? 9 57 fg <8 567fg g> ,7bf4g @, 567fg 8 567fg > 567fg ?, 9 57 fg <- 567fg g,. ,.&fg @: 567fg - 567fg ,. 567fg ?: 567fg <+ 567fg g, 567fg @8 e + 9 57 fg , 567fg ?8 9 57 fg <7 e g,, 567fg @- 567fg 7 567fg ,, 567fg ?- e <= e 7 @+ 57.fg = 9 3 567fg ?+ 9 57 fg <> e , ,7bfg @7 567fg > )e 3, 567fg ?7 9 57 fg <. e : )e @= 567fg . 9 3: 567fg ?= 567fg < 567fg 8 567fg @> 567fg )e 38 567fg ?> 567fg <, e - 567fg @,. )e , 9 3- 567fg ?,. 57.fg <: 567fg + 567fg @, 9 , fg : 9 3+ 9 57 fg ?, e <8 e 7 e @,, 567fg 8 )e 37 )e ?,, 5e.fg <- 567fg = 5e.fg - 9 3= 567fg 0 567fg <+ e > e -,)/, !> !'@ 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" 8=8@; "" 5
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-+@;"3 %(,)/, ! -+@; "" -+@; "" -+@; "" -+@; "" -+@; "" -+@; "" )e # 57>@ 57>)@ ; e - 9 : 57>=@ , 57>@ #, e , 57>)@ ;, 5e.>)@ + 9 8 9 : 57>@ #: 57>@ : e ;: 57>)@ )e - 57>=@ 8 57>@ #8 ,7b>@ 8 9 , >4@ ;8 57>)@ , )e + 9 57 >=@ - e #- 57>@ - 57>@ ;- 57>)@ : )e )e + 57>@ #+ 57>@ + 57>@ ;+ 9 57 >)@ 8 )e , )e 7 57.>@ #7 57>@ 7 57>@ ;, 9 57 >@ - )e : )e = 57>@ #= 5e.>@ = 9 ;,, 57>@ + )e 8 )e > 57>@ #> 57>@ > e ;,: 57>@ , 9 - )e . 57>@ #. e . 57>@ ;,8 e ,, 57>@ + )e e # 57>@ 57>@ ;,- e ,: 57>@ , 9 57 >@ , 57>@ #, e , 9 ;,+ 5e.>@ ,8 e ,, 57>@ : 57>@ #: d>*@ : 57>@ e ,- 57>@ ,: 9 8 e #8 57>@ 8 57>@ , 57>)@ ,+ 57>@ ,8 e - 57>@ #- 57>@ - 57>@ : 57.>)@ e ,- e + 57>@ #+ 57>@ + 9 8 57>)@ , e ,+ .& 7 57>@ #7 e 7 d>(@ - 57>)@ : e e = 57.>@ #= 57>@ = 57>@ + 9 8 e , 57>=@ > 57.>@ #> 57>@ > e , 9 - 57>)@ : e ,. e #,. 57>@ ,. 57>@ ,, 9 + 9 57 >)@ 8 57>=@ , 57>@ #, 57>@ , e ,: 57>@ )e - 9 ,, e #,, 57>@ ,, e ,8 57.>@ , )e + 9 ,: 57>@ #,: 57>@ ,: )e,>@ ,- 57.>@ : )e )e ,8 57>@ #,8 57>@ ,8 57>@ ,+ 57>@ 8 )e , )e ,- ,.&>@ #,- 57>@ ,- 57>@ f e - )e : )e ,+ )e #,+ 57>@ ,+ 57>@ f, 57>)@ + )e 8 )e @ 57>@ 57>)@ 57.>)@ f: 57>)@ , 9 57 >@ - )e @, ,.&>4@ , 57>)@ , e f8 e ,, 9 + )e @: 57>@ : 57>@ : e f- 57>)@ ,: e , 9 @8 57>@ 8 e 8 e f+ 9 57 >)@ ,8 e ,, 57>@ @- 57>@ - )e,>4@ - 57>@ f, 9 57 >@ ,- 57>@ ,: e @+ 57>@ + 57>@ + )e f,, 57>@ ,+ e ,8 e @7 57.>@ 7 57>@ 7 9 57 >@ f,: 57>@ % d ,- e @= 57>@ = e = 9 f,8 e %, e ,+ 57>@ @> 57>@ > 57>@ > 9 57 >@ f,- 57>@ %: 57>)@ 3 e @. 57>@ . 57>@ . )e f,+ 57>@ %8 57>)@ 3, 57>=@ @ 57>@ 57>@ 9 6 e %- 57>)@ 3: 57>=@ @, 57>@ , e , 9 57 >@ 6, 57>)@ %+ )e 38 57>=@ @: d>%@<,5 e>@ : 0& : )e 6: 57>)@ % )e 3- e @8 57>@ 8 57>@ 8 9 57 >@ 68 57>)@ %, )e 3+ 9 @- 57>@ - 57>@ - 9 6- e %: )e 3 )e @+ 57>@ + e + 9 6+ )e %8 )e 3, )e @7 57>@ 7 57>@ 7 )e 6, )e %- )e 3: )e @= 5e.>@ = 57>@ = 9 57 >@ 6,, 57>@ %+ )e 38 )e @> 57>@ > d>-@ > 9 6,: 57>@ %, )e 3- )e @,. e ,. 57>@ ,. 9 57 >@ 6,8 e %,, 57>@ 3+ )e @, 57>@ , 57>@ , )e 6,- e %,: 57>@ 3, 9 @,, 57>@ ,, e ,, e 6,+ e %,8 e 3,, 9 @,: 57>@ ,: 9 , >@ ,: e 57>)@ %,- 57>@ 3,: e @,8 57>@ ,8 57>@ ,8 57>@ , e %,+ 57>@ 3,8 57>@ @,- 57>@ ,- 57>@ ,- e : 57>)@ e 3,- e @,+ ,7b>4@ ,+ e ,+ 57>@ 8 57>)@ , 57>=@ 3,+ 57>@ 5
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#""'" telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ " ) #/)
"'" copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this product brief, and the accompanying software programs are protected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic, quick works, pasic, and vialink are registered trademarks of quicklogic corporation. all trademarks and registered trademarks are the property of their respective owners. .# =! 1 " #" a april 2001 first release. b june 2002 added kfactor, power-up, jtag and mechanical drawing information.

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